Test Compression is a technique used as part of a Design For Test (“DFT”) method to reduce the time and cost of testing integrated circuits. Straightforward application of scan techniques can result in large vector sets with corresponding long tester time and memory requirements. Test Compression techniques address this problem, by decompressing the scan input on chip and compressing the test output. Test Compression allows highly compressed test stimuli to be applied from low-pin count testers and compressed test responses to be measured. Large gains are possible since any particular test vector usually only needs to set and/or examine a small fraction of the scan chain bits.
The first ICs were tested with test vectors created by hand. It proved very difficult to get good coverage of potential faults, so DFT based on scan and automatic test pattern generation (“ATPG”) were developed to explicitly test each gate and path in a design. These techniques were very successful at creating high-quality vectors for manufacturing test, with excellent test coverage. However, as chips got bigger the ratio of logic to be tested per input/output test pin increased dramatically. Accordingly, trying to input the huge volume of scan test sequences into the chip via only a fixed (and often very minimal) number of test pins started causing a significant increase in test time, and required tester memory. This raised the cost of testing.
Test Compression was developed to help address this problem. When an ATPG tool generates a scan chain for a fault, or a set of faults, only a small percentage of scan cells in the scan chain need to take specific values. The rest of the cells in the scan chain are “don't care”, and are usually filled with random values. Scan chains are typically loaded by shifting them into the registers 1 bit per clock cycle and thus, the longer the scan chain the more time it takes to load. Loading and unloading long scan chains, also known as vectors, is not a very efficient use of tester time.
Test Compression takes advantage of the small number of significant values to reduce test data and test time. In general, the idea is to modify the design to increase the number of internal scan chains, each of shorter length. Shorter chain lengths reduce the test data volume as well as the test application time.
The scan chains are driven by an on-chip Compression logic and observed on the output side by an on-chip Decompressor. For example a Decompressor is usually designed to allow continuous flow decompression where the internal scan chains are loaded as the test response data from the previous test is delivered to the Decompressor. The Compression DFT logic is traditionally located in a single location on the chip. Accordingly, increased Compression DFT logic creates a higher scan wiring congestion as more wires need to be routed to and from the Compression DFT logic to support the shorter scan chains. Impact on congestion can be extreme for compression ratios beyond 100× since lots of wires terminate and originate from a small piece of compression logic. Traditional global placement has been found to be insufficient in many cases to route the scan wiring. It has been observed that back-end tools cannot impact structuring of Test Compression logic to mitigate congestion since there are too many restrictions in the construction of the scan chains as described in the ScanDEF format. Methods such as improved XOR mapping, partitioned Compressor-Decompressors (CoDecs), etc., are mainly incremental fixes.
Chips continue to increase in size and sophistication at accelerating rates. Every technology node has seen an increase in test data volume due to the higher gate counts and more advanced fault modeling. Increasing demand for rapid ramp up to high volume while maintaining low defective parts per million (“DPPM”) is leading to more investment in Test Compression technology. A survey of leading edge DFT customers has led to the conclusion that a 5-10× increase in compression efficiency is a pressing need. Accordingly, there is a need for a highly efficient, correct-by-construction and predictable method that supports increasing compression ratios including those over 500×.